A host computer system often communicates with computer memory such as DRAMs (Dynamic Random Access Memory) via a memory controller that issues commands to DRAM modules. In a typical memory controller, the commands indicate the memory location to be read or written, and are synchronized by a clock at the memory controller. Another clocking scheme at the DRAM orders the retrievals and also maintains the values in the DRAM, as non-volatile memory such as DRAM relies on consistent signals (i.e. voltage) to maintain the values (bits) in memory.
Conventional memory accesses travel via electrical signals between the memory controller and the DRAM modules, typically via a connection called a bus. Due to the high speed of these accesses, resulting from a clock speed of the memory controller and the bus nature of the link connecting memory controller and multiple DRAMs, individual DRAM results are queued and retimed to account for latency requirements between the commands to different DRAMs and the corresponding results (fetched data) to prevent data congestion at the bus. Such queues, or FIFOs (First-In-First-Out), order the results to maintain synchronization and timing between the commands requesting memory and the corresponding results of fetched memory values on DRAM component level